SRAM (Static Random Access Memory) is a form of volatile memory commonly used for short term, high speed storage. SRAM offers high speed in exchange for high cost and high power consumption compared to many other memory types. It is frequently used as cache memory in processors of many different types, such as central processing units, graphics processors, and controllers. It is also used for caches and buffers in communications interfaces, video interfaces, and signal processors. SRAM is frequently integrated onto the same die with a processor and therefore fabricated using the same technologies, such as CMOS (Complementary Metal Oxide Semiconductor).
As processing circuitry shrinks and operates at lower power, the design margin for SRAM continues to shrink. SRAM bitcells have been produced smaller than 0.1 μm2 using 22 nm technology. The consistency and yield of SRAM arrays, however, has declined. In part this is due to increased variation in produced dies. As the components on the die shrink, the same production variations become larger in comparison to the components. These variations mean that some SRAM cells have a higher minimum operating voltage than others on the same die. The reduced size and reduced operating voltages have also reduced the difference between the read voltage and the write voltage.
Die to die variations (variations between dies produced at the same time on a single wafer) result in some dies being limited by a minimum read voltage, while other dies are limited by a minimum write voltage. A slow N (N-type MOS (Metal Oxide Semiconductor) switching voltage) fast P (P-type MOS switching voltage) die would be write limited while a fast N slow P die would be read limited. Operating temperature also affects the characteristics of each die. Many die that are write limited at cold temperatures may be read limited at hot temperatures.
Word-Line Under-Drive (WLUD) has been proposed to improve the VCCmin (minimum operating voltage or Common-Collector Voltage) margin of a memory bitcell. Under-driving the word-line during memory access reduces the effective gate drive thus enhancing read stability. However, WLUD degrades cell writabilty and so increases VCCmin for write operations. In addition, due to the die to die variations and variations within a particular die, the best WLUD to use for different SRAM bitcells or SRAM arrays can be very different. For dies that are fabricated on different wafers, the differences can be still greater. For best performance, each die is characterized independently, however this adds to the production test-time and cost. Shifts in read/write balance due to temperature changes will also have to be characterized. This further increases test-time. In addition, a read-write assist setting will have to chosen that helps meet goals at both low and high temperatures.
Smart and adaptive assist circuits have been introduced to open up the design margin as well as to meet power and performance specifications. VCC scaling is especially important to meet the increasingly stringent power requirements. Although read stability is a major factor limiting voltage scaling for high density SRAM cells, the design window between read stability and the write margin is steadily decreasing and a significant number of SRAM cells can be write limited in a high volume manufacturing environment.